This invention relates to an oscillator circuit which is useful in providing a 50% duty cycle and is designed to prevent latch-up.
Latch-up may occur in an oscillator if the external timing capacitor starts discharging before the voltage limits have been switched. What can occur is, if the timing capacitor is charging and eventually reaches its upper limit it would start to discharge. If it gets below the upper limit before the limit has been changed, then the capacitor will start charging again towards the upper limit. It is therefore necessary to insure that the limits are switched before the direction of the timing capacitor is reversed. Some oscillators incorporate on-board flip-flops to insure a latch free operation. While this method works, it requires more complex circuitry to achieve the desired result. It is an object of the present invention to accomplish a latch-free operation with only two diodes and a transistor to perform the essential task.
Most oscillators use a network of two resistors and one capacitor to set the oscillator timing. While this method is good for achieving variable duty cycles, a considerable error is added into the system when a 50% duty cycle is required. It is an object of the present invention to provide a near ideal 50% duty cycle by charging and discharging the timing capacitor through a single resistor.